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CAT28LV256
Page Write
The page write mode of the CAT28LV256 (essentially
an extended BYTE WRITE mode) allows from 1 to 64
bytes of data to be programmed within a single E 2 PROM
write cycle. This effectively reduces the byte-write time
by a factor of 64.
Following an initial WRITE operation ( WE pulsed low, for
t WP , and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a 64 byte temporary buffer. The page
address where data is to be written, specified by bits A 6
to A 14 , is latched on the last falling edge of WE . Each
byte within the page is defined by address bits A 0 to A 5
Figure 5. Byte Write Cycle [ CE Controlled]
ADDRESS
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within t BLC MAX of the rising edge of the
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within t BLC MAX .
Upon completion of the page write sequence, WE must
stay high a minimum of t BLC MAX for the internal auto-
matic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
which writes new data back into the cell. A page write will
only write data to the locations that were addressed and
will not rewrite the entire page.
tWC
tAS
tAH
tBLC
tCW
CE
tOEH
OE
tCS
tOES
tCH
WE
HIGH-Z
DATA OUT
DATA IN
DATA VALID
tDS
tDH
28LV256 F08
Figure 6. Page Mode Write Cycle
OE
CE
t WP
t BLC
WE
ADDRESS
t WC
I/O
LAST BYTE
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
BYTE n+2
28LV256 F09
? 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
7
Doc. No. MD-1071, Rev. E
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